#ifndef REG_DMACV2_TYPE_H_
#define REG_DMACV2_TYPE_H_
#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef struct
{
    volatile uint32_t CSR; //0x20
    volatile uint32_t SAR; //0x24
    volatile uint32_t DAR; //0x28
    volatile uint32_t BCR; //0x2c
}reg_dmac_ch_t;

typedef struct
{
    volatile uint32_t IER; //0x0
    volatile uint32_t IDR; //0x4
    volatile uint32_t IVS; //0x8
    volatile uint32_t RIF; //0xc
    volatile uint32_t IFM; //0x10
    volatile uint32_t ICR; //0x14
    volatile uint32_t EMSG; //0x18
    volatile uint32_t RESERVED0[1];
    reg_dmac_ch_t     CH[DMAC_CHANNEL_NUM];
}reg_dmac_t;

enum DMAC_REG_IER_FIELD
{
    DMAC_CH0BTDIE_MASK = (int)0x1,
    DMAC_CH0BTDIE_POS = 0,
    DMAC_CH0TABIE_MASK = (int)0x2,
    DMAC_CH0TABIE_POS = 1,
    DMAC_CH1BTDIE_MASK = (int)0x4,
    DMAC_CH1BTDIE_POS = 2,
    DMAC_CH1TABIE_MASK = (int)0x8,
    DMAC_CH1TABIE_POS = 3,
    DMAC_CH2BTDIE_MASK = (int)0x10,
    DMAC_CH2BTDIE_POS = 4,
    DMAC_CH2TABIE_MASK = (int)0x20,
    DMAC_CH2TABIE_POS = 5,
    DMAC_CH3BTDIE_MASK = (int)0x40,
    DMAC_CH3BTDIE_POS = 6,
    DMAC_CH3TABIE_MASK = (int)0x80,
    DMAC_CH3TABIE_POS = 7,
    DMAC_CH4BTDIE_MASK = (int)0x100,
    DMAC_CH4BTDIE_POS = 8,
    DMAC_CH4TABIE_MASK = (int)0x200,
    DMAC_CH4TABIE_POS = 9,
    DMAC_CH5BTDIE_MASK = (int)0x400,
    DMAC_CH5BTDIE_POS = 10,
    DMAC_CH5TABIE_MASK = (int)0x800,
    DMAC_CH5TABIE_POS = 11,
};

enum DMAC_REG_IDR_FIELD
{
    DMAC_CH0BTDID_MASK = (int)0x1,
    DMAC_CH0BTDID_POS = 0,
    DMAC_CH0TABID_MASK = (int)0x2,
    DMAC_CH0TABID_POS = 1,
    DMAC_CH1BTDID_MASK = (int)0x4,
    DMAC_CH1BTDID_POS = 2,
    DMAC_CH1TABID_MASK = (int)0x8,
    DMAC_CH1TABID_POS = 3,
    DMAC_CH2BTDID_MASK = (int)0x10,
    DMAC_CH2BTDID_POS = 4,
    DMAC_CH2TABID_MASK = (int)0x20,
    DMAC_CH2TABID_POS = 5,
    DMAC_CH3BTDID_MASK = (int)0x40,
    DMAC_CH3BTDID_POS = 6,
    DMAC_CH3TABID_MASK = (int)0x80,
    DMAC_CH3TABID_POS = 7,
    DMAC_CH4BTDID_MASK = (int)0x100,
    DMAC_CH4BTDID_POS = 8,
    DMAC_CH4TABID_MASK = (int)0x200,
    DMAC_CH4TABID_POS = 9,
    DMAC_CH5BTDID_MASK = (int)0x400,
    DMAC_CH5BTDID_POS = 10,
    DMAC_CH5TABID_MASK = (int)0x800,
    DMAC_CH5TABID_POS = 11,
};

enum DMAC_REG_IVS_FIELD
{
    DMAC_CH0BTDIVS_MASK = (int)0x1,
    DMAC_CH0BTDIVS_POS = 0,
    DMAC_CH0TABIVS_MASK = (int)0x2,
    DMAC_CH0TABIVS_POS = 1,
    DMAC_CH1BTDIVS_MASK = (int)0x4,
    DMAC_CH1BTDIVS_POS = 2,
    DMAC_CH1TABIVS_MASK = (int)0x8,
    DMAC_CH1TABIVS_POS = 3,
    DMAC_CH2BTDIVS_MASK = (int)0x10,
    DMAC_CH2BTDIVS_POS = 4,
    DMAC_CH2TABIVS_MASK = (int)0x20,
    DMAC_CH2TABIVS_POS = 5,
    DMAC_CH3BTDIVS_MASK = (int)0x40,
    DMAC_CH3BTDIVS_POS = 6,
    DMAC_CH3TABIVS_MASK = (int)0x80,
    DMAC_CH3TABIVS_POS = 7,
    DMAC_CH4BTDIVS_MASK = (int)0x100,
    DMAC_CH4BTDIVS_POS = 8,
    DMAC_CH4TABIVS_MASK = (int)0x200,
    DMAC_CH4TABIVS_POS = 9,
    DMAC_CH5BTDIVS_MASK = (int)0x400,
    DMAC_CH5BTDIVS_POS = 10,
    DMAC_CH5TABIVS_MASK = (int)0x800,
    DMAC_CH5TABIVS_POS = 11,
};

enum DMAC_REG_RIF_FIELD
{
    DMAC_CH0BTDRIF_MASK = (int)0x1,
    DMAC_CH0BTDRIF_POS = 0,
    DMAC_CH0TABRIF_MASK = (int)0x2,
    DMAC_CH0TABRIF_POS = 1,
    DMAC_CH1BTDRIF_MASK = (int)0x4,
    DMAC_CH1BTDRIF_POS = 2,
    DMAC_CH1TABRIF_MASK = (int)0x8,
    DMAC_CH1TABRIF_POS = 3,
    DMAC_CH2BTDRIF_MASK = (int)0x10,
    DMAC_CH2BTDRIF_POS = 4,
    DMAC_CH2TABRIF_MASK = (int)0x20,
    DMAC_CH2TABRIF_POS = 5,
    DMAC_CH3BTDRIF_MASK = (int)0x40,
    DMAC_CH3BTDRIF_POS = 6,
    DMAC_CH3TABRIF_MASK = (int)0x80,
    DMAC_CH3TABRIF_POS = 7,
    DMAC_CH4BTDRIF_MASK = (int)0x100,
    DMAC_CH4BTDRIF_POS = 8,
    DMAC_CH4TABRIF_MASK = (int)0x200,
    DMAC_CH4TABRIF_POS = 9,
    DMAC_CH5BTDRIF_MASK = (int)0x400,
    DMAC_CH5BTDRIF_POS = 10,
    DMAC_CH5TABRIF_MASK = (int)0x800,
    DMAC_CH5TABRIF_POS = 11,
};

enum DMAC_REG_IFM_FIELD
{
    DMAC_CH0BTDIFM_MASK = (int)0x1,
    DMAC_CH0BTDIFM_POS = 0,
    DMAC_CH0TABIFM_MASK = (int)0x2,
    DMAC_CH0TABIFM_POS = 1,
    DMAC_CH1BTDIFM_MASK = (int)0x4,
    DMAC_CH1BTDIFM_POS = 2,
    DMAC_CH1TABIFM_MASK = (int)0x8,
    DMAC_CH1TABIFM_POS = 3,
    DMAC_CH2BTDIFM_MASK = (int)0x10,
    DMAC_CH2BTDIFM_POS = 4,
    DMAC_CH2TABIFM_MASK = (int)0x20,
    DMAC_CH2TABIFM_POS = 5,
    DMAC_CH3BTDIFM_MASK = (int)0x40,
    DMAC_CH3BTDIFM_POS = 6,
    DMAC_CH3TABIFM_MASK = (int)0x80,
    DMAC_CH3TABIFM_POS = 7,
    DMAC_CH4BTDIFM_MASK = (int)0x100,
    DMAC_CH4BTDIFM_POS = 8,
    DMAC_CH4TABIFM_MASK = (int)0x200,
    DMAC_CH4TABIFM_POS = 9,
    DMAC_CH5BTDIFM_MASK = (int)0x400,
    DMAC_CH5BTDIFM_POS = 10,
    DMAC_CH5TABIFM_MASK = (int)0x800,
    DMAC_CH5TABIFM_POS = 11,
};

enum DMAC_REG_ICR_FIELD
{
    DMAC_CH0BTDICR_MASK = (int)0x1,
    DMAC_CH0BTDICR_POS = 0,
    DMAC_CH0TABICR_MASK = (int)0x2,
    DMAC_CH0TABICR_POS = 1,
    DMAC_CH1BTDICR_MASK = (int)0x4,
    DMAC_CH1BTDICR_POS = 2,
    DMAC_CH1TABICR_MASK = (int)0x8,
    DMAC_CH1TABICR_POS = 3,
    DMAC_CH2BTDICR_MASK = (int)0x10,
    DMAC_CH2BTDICR_POS = 4,
    DMAC_CH2TABICR_MASK = (int)0x20,
    DMAC_CH2TABICR_POS = 5,
    DMAC_CH3BTDICR_MASK = (int)0x40,
    DMAC_CH3BTDICR_POS = 6,
    DMAC_CH3TABICR_MASK = (int)0x80,
    DMAC_CH3TABICR_POS = 7,
    DMAC_CH4BTDICR_MASK = (int)0x100,
    DMAC_CH4BTDICR_POS = 8,
    DMAC_CH4TABICR_MASK = (int)0x200,
    DMAC_CH4TABICR_POS = 9,
    DMAC_CH5BTDICR_MASK = (int)0x400,
    DMAC_CH5BTDICR_POS = 10,
    DMAC_CH5TABICR_MASK = (int)0x800,
    DMAC_CH5TABICR_POS = 11,
};

enum DMAC_REG_EMSG_FIELD
{
    DMAC_CH0SETBCER_MASK = (int)0x1,
    DMAC_CH0SETBCER_POS = 0,
    DMAC_CH0SETBUER_MASK = (int)0x2,
    DMAC_CH0SETBUER_POS = 1,
    DMAC_CH0PFOV_MASK = (int)0x4,
    DMAC_CH0PFOV_POS = 2,
    DMAC_CH0PFSER_MASK = (int)0x8,
    DMAC_CH0PFSER_POS = 3,
    DMAC_CH1SETBCER_MASK = (int)0x10,
    DMAC_CH1SETBCER_POS = 4,
    DMAC_CH1SETBUER_MASK = (int)0x20,
    DMAC_CH1SETBUER_POS = 5,
    DMAC_CH1PFOV_MASK = (int)0x40,
    DMAC_CH1PFOV_POS = 6,
    DMAC_CH1PFSER_MASK = (int)0x80,
    DMAC_CH1PFSER_POS = 7,
    DMAC_CH2SETBCER_MASK = (int)0x100,
    DMAC_CH2SETBCER_POS = 8,
    DMAC_CH2SETBUER_MASK = (int)0x200,
    DMAC_CH2SETBUER_POS = 9,
    DMAC_CH2PFOV_MASK = (int)0x400,
    DMAC_CH2PFOV_POS = 10,
    DMAC_CH2PFSER_MASK = (int)0x800,
    DMAC_CH2PFSER_POS = 11,
    DMAC_CH3SETBCER_MASK = (int)0x1000,
    DMAC_CH3SETBCER_POS = 12,
    DMAC_CH3SETBUER_MASK = (int)0x2000,
    DMAC_CH3SETBUER_POS = 13,
    DMAC_CH3PFOV_MASK = (int)0x4000,
    DMAC_CH3PFOV_POS = 14,
    DMAC_CH3PFSER_MASK = (int)0x8000,
    DMAC_CH3PFSER_POS = 15,
    DMAC_CH4SETBCER_MASK = (int)0x10000,
    DMAC_CH4SETBCER_POS = 16,
    DMAC_CH4SETBUER_MASK = (int)0x20000,
    DMAC_CH4SETBUER_POS = 17,
    DMAC_CH4PFOV_MASK = (int)0x40000,
    DMAC_CH4PFOV_POS = 18,
    DMAC_CH4PFSER_MASK = (int)0x80000,
    DMAC_CH4PFSER_POS = 19,
    DMAC_CH5SETBCER_MASK = (int)0x100000,
    DMAC_CH5SETBCER_POS = 20,
    DMAC_CH5SETBUER_MASK = (int)0x200000,
    DMAC_CH5SETBUER_POS = 21,
    DMAC_CH5PFOV_MASK = (int)0x400000,
    DMAC_CH5PFOV_POS = 22,
    DMAC_CH5PFSER_MASK = (int)0x800000,
    DMAC_CH5PFSER_POS = 23,
};

enum DMAC_REG_CSR_FIELD
{
    DMAC_CHEN_MASK = (int)0x1,
    DMAC_CHEN_POS = 0,
    DMAC_CIRC_MASK = (int)0x2,
    DMAC_CIRC_POS = 1,
    DMAC_PFCTRL_MASK = (int)0x4,
    DMAC_PFCTRL_POS = 2,
    DMAC_DIRMDEN_MASK = (int)0x8,
    DMAC_DIRMDEN_POS = 3,
    DMAC_MODESEL_MASK = (int)0x30,
    DMAC_MODESEL_POS = 4,
    DMAC_CHPRI_MASK = (int)0x1c0,
    DMAC_CHPRI_POS = 6,
    DMAC_PHSS_MASK = (int)0xfe00,
    DMAC_PHSS_POS = 9,
    DMAC_SINC_MASK = (int)0x10000,
    DMAC_SINC_POS = 16,
    DMAC_SDWSEL_MASK = (int)0x60000,
    DMAC_SDWSEL_POS = 17,
    DMAC_SBUSEL_MASK = (int)0x380000,
    DMAC_SBUSEL_POS = 19,
    DMAC_SINCOS_MASK = (int)0x400000,
    DMAC_SINCOS_POS = 22,
    DMAC_DINC_MASK = (int)0x1000000,
    DMAC_DINC_POS = 24,
    DMAC_DDWSEL_MASK = (int)0x6000000,
    DMAC_DDWSEL_POS = 25,
    DMAC_DBUSEL_MASK = (int)0x38000000,
    DMAC_DBUSEL_POS = 27,
    DMAC_DINCOS_MASK = (int)0x40000000,
    DMAC_DINCOS_POS = 30,
};

enum DMAC_REG_BCR_FIELD
{
    DMAC_BCR_MASK = (int)0xffff,
    DMAC_BCR_POS = 0,
    DMAC_CBCR_MASK = (int)0xffff0000,
    DMAC_CBCR_POS = 16,
};

#ifdef __cplusplus
}
#endif

#endif

